Without limiting the scope of the invention, its background is described in connection with a system which implements a system interface bus which couples devices in parallel, and in connection with an output buffer circuit for use on devices coupled to a bus. The system is further described using a SCSI (Small Computer System Interface) bus as an example.
Interfacing digital systems has become increasingly difficult for the designer due to the emphasis on high-speed performance. The high-speed performance of most digital systems is now limited by distributed discontinuities and transmission line effects of packaging and interconnects, and not by the switching speed of semiconductor devices. It is becoming increasingly common for digital systems to be interfaced with electrically long cables comprised of bundled-wire or fiat-wire connections. These applications are typically found in personal computers and workstations where connection to external peripheral equipment, such as disk drives, scanners, or printers, is implemented with user installed cables.
Problems are encountered when signal line reflections and high frequency ringing cause data read errors on the interface bus. The primary cause of this poor data quality is the rapid slew-rate of the I/O port output driver circuits. Typical prior art output circuits exhibit signal transition slew rates of 3 V/nsec. This rapid rate of change on the signal line will excite the resonant frequency of the bus cable as well as contribute to the strength of signal reflections. The dilemma for the prior art system designer has been that the exact characteristics of the bus signal noise cannot be predicted due to variations in physical cable length and connector impedance mismatch, and hence, signal line tuning cannot be applied to solve the problem. When the rise and fall times of the signal pulses are less than the propagation delay of the cable, transmission line effects become a serious problem to contend with. Proper design of cable terminations will eliminate some of the signal noise, however, the most dramatic reduction of these transmission line effects is achieved by making the rise and fall times of the signal pulses much slower. Controlling the slew rate of the signal driver circuit is therefore critically important in minimizing transmission line noise.
Current technologies used for digital systems bus interface include circuits designed using digital and linear CMOS processes, and digital Bi-CMOS processes. Controlled slew-rate drivers have been developed in linear CMOS and digital Bi-CMOS technologies, however these technologies are cost prohibitive, and the resulting designs typically exhibit undesirably complex circuitry as well as measurable standby power dissipation. The digital CMOS technology is attractive for bus interface driver designs due to its cost effectiveness, leakage-level standby current flow, and popularity in digital subsystems design. However, controlled slew-rate designs are very difficult to develop in digital CMOS technologies. Prior art controlled slew-rate designs utilize some form of output feed-back, and digital CMOS technology lacks the commonly used features of either the bipolar technology's junction transistors, or the linear technology's precision resistors and capacitors. Controlled slew-rate driver designs implemented without these elements exhibit widely varying performance parameters over the range of operating conditions, and hence have not been viable solutions for practical bus interface performance requirements.
Bus interface methodologies that incorporate active pull-down "open-drain" wire-ANDed driver outputs offer a partial solution by using the bus termination circuitry to passively control the low-to-high signal transition slew-rate. An example of this application is the SCSI (Small Computer System Interface) bus. This type of bus implementation, however, still exhibits undesirable transmission line noise produced by the high rate of change of the high-to-low signal transition of the prior art bus driver circuits. Accordingly, a bus driver circuit design that can be implemented in a standard digital CMOS technology as an element of an integrated circuit, and having improvements that overcome any or all of the problems of the prior art solutions, is presently desirable.